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Employment Type: Full-Time
Work Setting: Remote
Work Location: Korea
Work Hours: Office hours
Find out more here:
About SemiAnalysis
SemiAnalysis is an independent research and analysis firm specializing in the Semiconductor and AI industries. Our in-depth coverage spans the entire supply chain, from semiconductor fabrication processes to cutting-edge AI Models, software, and infrastructure. We are recognized as the leading authority on the semiconductor supply chain, with the highest concentration of industry experts within one team, and a deep-rooted passion for delving into the intricacies.
We’re a global team of over 50 analysts, each with extensive networks across the semiconductor supply chain and AI ecosystem, publishing industry‑shaping articles while participating in 40+ conferences annually.
Our newsletter reaches more than 200 000 subscribers worldwide, including senior management and C‑suite leaders at the leading semiconductor and AI companies.
We also offer three core products:
Industry Models – we develop and publish industry models on accelerator shipments, datacenter demand and supply, GPU total cost of ownership, and more. We work with hyperscalers, neoclouds, many of the world’s largest hedge funds, and government agencies.
Core Research – our public equity markets product, geared towards financial investors, distills our deep technical research and knowledge into key insights on technology and product trends.
Consulting and Technical Due Diligence – We conduct custom research and project work to guide key strategic and investment decisions for the largest private‑equity funds, leading venture‑capital firms, companies across the AI ecosystem, and government agencies.
Position Overview
We are seeking a Memory Technology Analyst focused on the process engineering, manufacturing technologies, and product roadmaps underpinning the DRAM, HBM, and NAND industries.
You will serve as our authority on memory process technology, assessing node transitions, scaling bottlenecks, packaging innovation, manufacturing economics, and vendor-by-vendor execution.
Your work will translate complex technical developments into differentiated research for institutional clients and provide critical inputs into our Memory Model , Accelerator & HBM Model , and Wafer Fab Equipment Model .
This role is suited to someone who can move comfortably between semiconductor process technology, manufacturing execution, cost structures, and investment implications.
Responsibilities
DRAM Process Technology
Analyze and forecast DRAM process-technology roadmaps across major memory manufacturers.
Evaluate capacitor-scaling limits, high-k/metal-gate integration, and other key process-integration challenges.
Track EUV insertion by process layer, technology node, and vendor.
Assess transitions toward 4F² cells, vertical-channel transistor architectures, and longer-term 3D DRAM approaches.
Evaluate how node transitions affect die size, wafer productivity, yield, cost per bit, and competitive positioning.
NAND Process Technology
Analyze and forecast NAND layer-count and string-stacking roadmaps.
Compare the manufacturing, yield, cost, and performance implications of each vendor’s technical approach.
Evaluate how architecture and process transitions influence bits per wafer, cycle times, capital intensity, and cost per bit.
HBM and Advanced Packaging
Assess HBM manufacturing and packaging technologies in depth.
Analyze TSV formation, wafer thinning, stacking, bonding, and interconnect approaches.
Track the transition from microbump-based packaging toward hybrid bonding.
Evaluate base-die transitions to external logic-foundry nodes.
Assess custom HBM architectures, stack-height transitions, known-good-die requirements, and test economics.
Identify manufacturing and packaging constraints that may affect HBM supply, yields, cost, and qualification timelines.
Competitive Benchmarking
Benchmark process-technology competitiveness across Samsung, SK hynix, Micron, Kioxia, SanDisk, CXMT, and YMTC.
Conduct die-size, bits-per-wafer, yield, and cost-per-bit analysis by node and product.
Assess vendor execution against publicly stated technology roadmaps and manufacturing targets.
Infer competitive positioning from technical disclosures, patents, academic papers, teardown data, and supplier commentary.
Equipment and Materials Analysis
Map memory-technology transitions to demand for wafer-fabrication equipment, materials, and process-control tools.
Work closely with SemiAnalysis ’ wafer-fab-equipment, foundry, packaging, and semiconductor research teams.
Identify potential winners and losers among equipment and materials suppliers.
Analyze how changes in process complexity, layer counts, lithography intensity, etch requirements, deposition steps, and bonding technologies affect supplier demand.
Research and Industry Coverage
Track memory-relevant developments presented at IEDM, ISSCC, VLSI, ECTC, and major vendor technology events.
Translate technical papers, presentations, patents, and disclosures into actionable research.
Serve as the technical counterpart to our memory-market analysts.
Pressure-test supply-model assumptions related to node-migration timing, yield ramps, wafer-capacity conversions, and production readiness.
Author and contribute to major research publications, technical reports, client notes, and newsletter deep dives.
Present technical findings to institutional investors, semiconductor companies, and other sophisticated industry participants.
Requirements
3+ years of experience in process engineering, process integration, research and development, yield engineering, or a closely related semiconductor-manufacturing role.
Relevant experience at a memory manufacturer, semiconductor-equipment supplier, materials company, technical research organization, or comparable industry-analysis firm.
Deep functional knowledge of DRAM and/or NAND process flows.
Strong understanding of front-end-of-line and back-end-of-line semiconductor manufacturing.
Knowledge of memory-specific process-integration challenges, including:
Capacitor formation and scaling.
High-aspect-ratio etch.
Channel-hole scaling.
High-k/metal-gate integration.
TSV formation.
Wafer thinning and stacking.
Bonding and interconnect technologies.
Understanding of advanced packaging as applied to memory, including TSVs, microbumps, hybrid bonding, stacking, test, and known-good-die economics.
Ability to evaluate competitive positioning using technical disclosures, conference papers, patents, teardown data, and manufacturing evidence.
Ability to connect process changes to yield, cycle time, die size, wafer productivity, cost per bit, and capital intensity.
Strong written and verbal communication skills.
Ability to explain complex process technologies and their economic implications to a sophisticated but non-specialist audience.
Full professional proficiency in English.
Preferred Skills
Korean-language proficiency.
Existing professional relationships across Korean memory fabs, equipment suppliers, packaging companies, and materials manufacturers.
Hands-on experience working in a semiconductor fab or process-development environment.
Familiarity with semiconductor analytical and failure-analysis techniques.
Ability to interpret SEM and TEM micrographs, cross-sectional analysis, electrical-test data, and physical teardown results.
Familiarity with memory die and stack cost modeling, including wafer cost, die size, yield, test, assembly, packaging, and bonding.